KAC-9627【PDF 11/41 页】IC SENSOR IMAGE VGA 48CLCC

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IMAGE SENSOR SOLUTIONS

Functional Description

1.0

OVERVIEW

After gain and color gain adjustment the analog value of each

pixel is converted to 12 bit digital data as shown in Figure .

1.1 Light Capture and Conversion

The KAC-9627 contains a CMOS active pixel array consisting of

0-14dB

648 columns, 488 rows

488 rows by 648 columns. This active region is surrounded by 8

columns and 8 rows of optically shielded (black) pixels as shown

in Figure7.

8 columns, 8 rows

black pixels

color (Bayer pattern) active pixels

0-15dB

Video

AMP

R

0-14dB

G

0-14dB

B

MUX

12 Bit A/D

Analog pixel values

Digital pixel data

Analog Signals Conditioning & Conversion to Digital

The digital pixel data is further processed to:

? remove defects due to bad pixels,

? compensate black level, before being framed and presented

on the digital output port. (see Figure 9).

do[11:0]

8 columns, 8 rows

black pixels

Figure 7: CMOS APS region of the KAC-9627

The color filters are Bayer pattern coded starting at row 8 and

column 8. (rows 0 to 7 & columns 0 to 7 are black). The color

coding is green, red, green, red until the end of row 8, then blue,

green, blue, green until the end or row 9 and so on (see Figure

7).

At the beginning of a given integration time the on-board timing

and control circuit will reset every pixel in the array one row at a

time as shown in Figure 8

pclk

hsync

vsync

Figure 9. Digital Pixel Processing.

1.2 Program and Control Interfaces

The programming, control and status monitoring of the KAC-

9627 is achieved through a two wire I 2 C compatible serial bus.

In addition, a slave address pin is provided (see Figure 10).

sda

Note that all pixels in the same row are simultaneously reset, but

not all pixels in the array

Register Bank

I 2 C Compatible

Serial I/F

sclk

0

1

a b c d e f g h i

j

k l m n o p q r

sadr

2

3

4

5

Analog Data Out

6

7

8

9

10

11

12

13

14

15

Figure 10. Control Interface to the KAC-9627.

Additional control and status pins: snapshot and external event

synchronization are provided allowing the latency of the serial

control port to be bypassed during single frame capture. An

interrupt request pin is also available allowing complex snapshot

operations to be controlled via an external micro-processor (see

Figure 11).

CDS/Shift Register

Figure 8. Sensor Addressing Scheme

At the end of the integration time, the timing and control circuit

will address each row and simultaneously transfer the integrated

Timing

Generator

extsyn

snapshot

value of the pixel to a correlated double sampling circuit and

then to a shift register as shown in Figure 8.

Once the correlated double sampled data has been loaded into

the shift register, the timing and control circuit will shift them out

one pixel at a time starting with column “a”.

The pixel data is then fed into an analog video amplifier, where a

user programmed gain is applied, then to the color amplifiers

(red, green, blue), where each color gain can be individually

adjusted (see Figure ).

Figure 11. Snapshot & External Event Trigger Signals

www.kodak.com/go/imagers 585-722-4385

11

Email:imagers@kodak.com

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